Modern semiconductor packages are formed from multiple stacked material layers that may include numerous active devices electrically coupled together by conductive metal interconnects and lines. High speed semiconductor devices can be formed using a combination of copper interconnects with suitable dielectric materials or films such as low-k dielectrics to take advantage of the superior conductivity of copper and reduced parasitic capacitance between the conductors.
Back end-of-line (“BEOL”) fabrication processes are used to create an intricate network of conductive interconnects in each layer and between the multiple layers. An additive patterning process referred to as “dual damascene” is one BEOL process used to form patterned copper conductor circuits in chip packages which interconnect various active components (e.g., resistors, transistors, etc.) disposed in single and multiple layers throughout the chip. Some of these interconnect circuit structures include within-layer trenches or lines filled with the copper to form circuits within a layer and between-layer vias which are essentially metal-plated or filled holes that electrically connect circuits between devices in the multiple layers of the semiconductor package.
As semiconductor technology pushes to 14 nanometer (N14) and below scale, the via resistance (Rc) yield window suffers caused by worsening via CDU (critical dimension uniformity) and OVL (overlay) inducing via under etch.
All drawings are schematic and are not drawn to scale.